@@ -123,7 +123,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
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// gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
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// PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
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pinMode (0 , INPUT);
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- pinMode ( 0 , FUNCTION_6 );
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+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 0 ], 5 );
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EMAC_EXT.ex_clk_ctrl .ext_en = 1 ;
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EMAC_EXT.ex_clk_ctrl .int_en = 0 ;
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EMAC_EXT.ex_oscclk_conf .clk_sel = 1 ;
@@ -135,7 +135,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
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// gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
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// PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
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pinMode (0 , OUTPUT);
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- pinMode ( 0 , FUNCTION_2 );
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+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 0 ], 1 );
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// Choose the APLL clock to output on GPIO
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REG_WRITE (PIN_CTRL, 6 );
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#endif
@@ -145,15 +145,15 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
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// gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
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// PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
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pinMode (16 , OUTPUT);
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- pinMode ( 16 , FUNCTION_6 );
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+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 16 ], 5 );
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#endif
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} else if (eth_clock_mode == ETH_CLOCK_GPIO17_OUT){
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#if CONFIG_ETH_RMII_CLK_OUT_GPIO != 17
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// RMII CLK (50MHz) output to GPIO17
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// gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
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// PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
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pinMode (17 , OUTPUT);
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- pinMode ( 17 , FUNCTION_6 );
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+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 17 ], 5 );
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#endif
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}
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#if CONFIG_ETH_RMII_CLK_INPUT
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