Intel's power limits are set via MSR+MMIO, but CoreFreq seems to only use MSR

[Betaminos]

I am seeing some weird behavior on my OXP (OneNetbook's OneXPlayer), which uses a Tiger Lake 1165g7. My CPU will throttle at the same power limit, regardless of how high I set it in COreFreq. Under Windows, there is a tool called Throttlestop that exposes the MSR and MMIO power limits which can both be used to limit the CPU's power. Unfortunately, the lower of the set power limits wins which means that only relying on the MSR limits can sometimes have no effect if the device is hitting limits set via MMIO.

After some digging, I have come across this script which seem to tackle MSR and MMIO nicely: https://github.com/horshack-dpreview/setPL

The trick (similar to Throttlestop) is to set the MMIO limit to unlimited and then disable them by setting the lock-bit. This way, the MSR limits are the only remaining ones and should be active.

If somehow possible, it would be great if CoreFreq would offer a button to set the MMIO-limits to unlimited and lock them afterwards, similar to this script. Alternatively, as the perfect solution, the MMIO limits could be displayed next to the MSR limits, to make tracing down the power limits a bit easier, which would be especially helpful in cases where the EC changes the MMIO power limits on the fly. (the latter can be killed by setting them to unlimited and locking them)

Thank you very much for your consideration :)

[cyring]

Let's start with some specs from latest gen datasheet

[cyring]

If somehow possible, it would be great if CoreFreq would offer a button to set the MMIO-limits to unlimited and lock them afterwards, similar to this script.

Do you have evidences that PKG_​PWR_​LIM_​LOCK (bit 63) as mentionned in script here is left unlocked by your BIOS ?

[Betaminos]

If somehow possible, it would be great if CoreFreq would offer a button to set the MMIO-limits to unlimited and lock them afterwards, similar to this script.

Do you have evidences that PKG_​PWR_​LIM_​LOCK (bit 63) as mentionned in script here is left unlocked by your BIOS ?

I have modified the script on my end to allow for read-only use and have added an additional echo before line 264.
The modified script can be found here: https://github.com/Betaminos/setPL/blob/master/setPL.sh

Its output is as follows:

!! Running SetPL in read-only mode !!
**** Current PL values from 'turbostat'
cpu0: MSR_PKG_POWER_LIMIT: 0x42014000dc80e0 (UNlocked)
cpu0: PKG Limit #1: ENabled (28.000 Watts, 28.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: DISabled (40.000 Watts, 0.002441* sec, clamp DIS
[setPLa.txt](https://github.com/cyring/CoreFreq/files/10931996/setPLa.txt)
abled)
**** PL1 and PL2 are DISabled in MSR_PKG_POWER_LIMIT
**** New PL values from 'turbostat'
cpu0: MSR_PKG_POWER_LIMIT: 0x42014000dc80e0 (UNlocked)
cpu0: PKG Limit #1: ENabled (28.000 Watts, 28.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: DISabled (40.000 Watts, 0.002441* sec, clamp DISabled)
**** MCHBAR is 0xfedc0001
**** Current value of PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU = 0x00428068:0x00dd8048
**** MMIO limit reg is NOT locked

Running the script with arguments after this gives:

sudo ./setPL.sh 10 12
**** Current PL values from 'turbostat'
cpu0: MSR_PKG_POWER_LIMIT: 0x42014000dc80e0 (UNlocked)
cpu0: PKG Limit #1: ENabled (28.000 Watts, 28.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: DISabled (40.000 Watts, 0.002441* sec, clamp DISabled)
**** Setting PL1=10000000 and PL2=12000000 in /sys/class/powercap/intel-rapl/intel-rapl:0/constraint_*_power_limit_uw
**** Enabling PL1 and PL2 in MSR_PKG_POWER_LIMIT
**** New PL values from 'turbostat'
cpu0: MSR_PKG_POWER_LIMIT: 0x42806000dc8050 (UNlocked)
cpu0: PKG Limit #1: ENabled (10.000 Watts, 28.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: ENabled (12.000 Watts, 0.002441* sec, clamp DISabled)
**** MCHBAR is 0xfedc0001
**** Current value of PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU = 0x00428068:0x00dd8048
**** MMIO limit reg is NOT locked
**** Setting PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU = 0x80000000:0x00000000

And on subsequent runs it will show that the MMIO limit reg is locked, as expected, leading me to believe that it is working:

sudo ./setPL.sh 9 9
**** Current PL values from 'turbostat'
cpu0: MSR_PKG_POWER_LIMIT: 0x42806000dc8050 (UNlocked)
cpu0: PKG Limit #1: ENabled (10.000 Watts, 28.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: ENabled (12.000 Watts, 0.002441* sec, clamp DISabled)
**** Setting PL1=9000000 and PL2=9000000 in /sys/class/powercap/intel-rapl/intel-rapl:0/constraint_*_power_limit_uw
**** PL1 and PL2 already ENabled in MSR_PKG_POWER_LIMIT
**** New PL values from 'turbostat'
cpu0: MSR_PKG_POWER_LIMIT: 0x42804800dc8048 (UNlocked)
cpu0: PKG Limit #1: ENabled (9.000 Watts, 28.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: ENabled (9.000 Watts, 0.002441* sec, clamp DISabled)
**** MCHBAR is 0xfedc0001
**** Current value of PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU = 0x80000000:0x00000000
**** MMIO limit reg locked with PL1/PL2 disabled on previous invocation (expected)

[cyring]

I don't miss a lot pf code to allow your feature.
Unlock bit was already part of the function as the PowerLimitLockMask argument and involved in PL conditions.

CoreFreq/corefreqk.c

Line 3589 in 150a219

void Intel_DomainPowerLimit( unsigned int MSR_DOMAIN_POWER_LIMIT,

However writing to the MMIO register is risky and can crash other models if unsupported.
That's why I need your hardware to program further.

[Betaminos]

Hi there and sorry, I did miss this more recent reply.
Happy to help - if you tell me what you need me to do on my device (TigerLake 1165g7).

[cyring]

Hi, thanks for helping

I'm wondering since when below MMIO registers are available on Intel architectures
If you can read/write PRIPTP SECPTP as will on your Tiger Lake ?
I beleive you can add their offset address to the obtained MCHBAR in setPL.sh source code; and attempt to alter from a few units

[cyring]

See :

13th Generation Intel® Core™

Processor
Datasheet, Volume 2 of 2
Formerly known as Raptor Lake-S Processor
October 2022
Revision 001

At chapter 3.3.16 :

Primary Plane Turbo Policy
(PRIP_TURBO_PLCY_0_0_0_MCHBAR_PCU) — Offset
5920h

Addr	Register
5920h	Priority Level (PRIPTP)
5924h	Priority Level (SECPTP)

[cyring]

These registers are found in:
11th Generation Intel® Core™
Processor
Datasheet Volume 2 of 2

Although it is mentioned:

Supporting 11th Generation Intel® Core™ Processor Families, Intel®
Server Processors, Intel® Work Station Processors for Desktop
Platform, formerly known as Rocket Lake

... those registers appear to work the same with Tiger Lake

For example in CoreFreq TGL_SA_PERF_STATUS at offset 5918h

CoreFreq/x86_64/intel_reg.h

Line 4557 in 3512685

{ /* Device: 0 - Function: 0 - Offset 5918h */

You can dig into the subsequent offsets starting from 0x5920

Also observe:

BIOS Mailbox Interface
(BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR_PCU) —
Offset 5DA4h

The bits layout is surprisingly same as the undocumented MSR MAILBOX

[cyring]

I have been able to lower the Package PL1/PL2 to 15/17 W
Using my stress Tools > Conic Compute I can verify that the undervolt is working on this TGL processor

[cyring]

Package Power Limit

(PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU) – Offset 59A0

• 12th Generation
• 13th Generation

[cyring]

Dev ceased