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Implement mips floating point related registers
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2 files changed

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‎include/unicorn/mips.h

+4
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,10 @@ typedef enum UC_MIPS_REG {
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UC_MIPS_REG_CP0_USERLOCAL,
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UC_MIPS_REG_CP0_STATUS,
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223+
// FCR(s) Ref: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00083-2B-MIPS64INT-AFP-06.01.pdf
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UC_MIPS_REG_FIR,
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UC_MIPS_REG_FCSR,
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UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
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225229
// alias registers

‎qemu/target/mips/unicorn.c

+94
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,49 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->active_tc.CP0_UserLocal;
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break;
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case UC_MIPS_REG_F0:
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case UC_MIPS_REG_F1:
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case UC_MIPS_REG_F2:
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case UC_MIPS_REG_F3:
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case UC_MIPS_REG_F4:
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case UC_MIPS_REG_F5:
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case UC_MIPS_REG_F6:
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case UC_MIPS_REG_F7:
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case UC_MIPS_REG_F8:
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case UC_MIPS_REG_F9:
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case UC_MIPS_REG_F10:
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case UC_MIPS_REG_F11:
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case UC_MIPS_REG_F12:
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case UC_MIPS_REG_F13:
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case UC_MIPS_REG_F14:
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case UC_MIPS_REG_F15:
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case UC_MIPS_REG_F16:
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case UC_MIPS_REG_F17:
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case UC_MIPS_REG_F18:
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case UC_MIPS_REG_F19:
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case UC_MIPS_REG_F20:
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case UC_MIPS_REG_F21:
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case UC_MIPS_REG_F22:
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case UC_MIPS_REG_F23:
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case UC_MIPS_REG_F24:
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case UC_MIPS_REG_F25:
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case UC_MIPS_REG_F26:
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case UC_MIPS_REG_F27:
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case UC_MIPS_REG_F28:
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case UC_MIPS_REG_F29:
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case UC_MIPS_REG_F30:
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case UC_MIPS_REG_F31:
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CHECK_REG_TYPE(uint64_t);
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*(uint64_t *)value = env->active_fpu.fpr[regid - UC_MIPS_REG_F0].d;
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break;
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case UC_MIPS_REG_FIR:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->active_fpu.fcr0;
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break;
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case UC_MIPS_REG_FCSR:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->active_fpu.fcr31;
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break;
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}
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}
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@@ -158,6 +201,57 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
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CHECK_REG_TYPE(mipsreg_t);
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env->active_tc.CP0_UserLocal = *(mipsreg_t *)value;
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break;
204+
case UC_MIPS_REG_F0:
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case UC_MIPS_REG_F1:
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case UC_MIPS_REG_F2:
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case UC_MIPS_REG_F3:
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case UC_MIPS_REG_F4:
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case UC_MIPS_REG_F5:
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case UC_MIPS_REG_F6:
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case UC_MIPS_REG_F7:
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case UC_MIPS_REG_F8:
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case UC_MIPS_REG_F9:
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case UC_MIPS_REG_F10:
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case UC_MIPS_REG_F11:
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case UC_MIPS_REG_F12:
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case UC_MIPS_REG_F13:
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case UC_MIPS_REG_F14:
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case UC_MIPS_REG_F15:
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case UC_MIPS_REG_F16:
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case UC_MIPS_REG_F17:
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case UC_MIPS_REG_F18:
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case UC_MIPS_REG_F19:
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case UC_MIPS_REG_F20:
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case UC_MIPS_REG_F21:
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case UC_MIPS_REG_F22:
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case UC_MIPS_REG_F23:
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case UC_MIPS_REG_F24:
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case UC_MIPS_REG_F25:
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case UC_MIPS_REG_F26:
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case UC_MIPS_REG_F27:
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case UC_MIPS_REG_F28:
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case UC_MIPS_REG_F29:
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case UC_MIPS_REG_F30:
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case UC_MIPS_REG_F31:
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CHECK_REG_TYPE(uint64_t);
237+
env->active_fpu.fpr[regid - UC_MIPS_REG_F0].d = *(uint64_t*)value;
238+
break;
239+
case UC_MIPS_REG_FCSR: {
240+
CHECK_REG_TYPE(uint32_t);
241+
uint32_t arg1 = *(uint32_t *)value;
242+
uint32_t original = env->active_fpu.fcr31;
243+
env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
244+
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
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if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
246+
GET_FP_CAUSE(env->active_fpu.fcr31)) {
247+
env->active_fpu.fcr31 = original;
248+
ret = UC_ERR_EXCEPTION;
249+
} else {
250+
restore_fp_status(env);
251+
set_float_exception_flags(0, &env->active_fpu.fp_status);
252+
}
253+
break;
254+
}
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}
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}
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