set pc_start on disasm

wtdcode · wtdcode · commit 2619b12cf0ae · 2025-02-10T21:28:23.000+08:00
diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c
@@ -452,7 +452,7 @@ static void gen_sub_carry(TCGContext *tcg_ctx, TCGv_i32 dest, TCGv_i32 t0, TCGv_
     tcg_gen_subi_i32(tcg_ctx, dest, dest, 1);
 }
 
-static inline void mb_tcg_opcode_cmp_hook(TCGContext *tcg_ctx, TCGv_i64 v0, TCGv_i64 v1, uint32_t size)
+static inline void mb_tcg_opcode_cmp_hook(TCGContext *tcg_ctx, TCGv_i64 v0, TCGv_i64 v1, uint32_t size, uint32_t pc)
 {
     uc_engine *uc = tcg_ctx->uc;
     if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_TCG_OPCODE, tcg_ctx->pc_start)) {
@@ -10925,6 +10925,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
 {
     unsigned int cond = insn >> 28;
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    tcg_ctx->pc_start = s->pc_curr;
 
     /* M variants do not implement ARM mode; this must raise the INVSTATE
      * UsageFault exception.

Original file line number	Diff line number	Diff line change
`@@ -452,7 +452,7 @@ static void gen_sub_carry(TCGContext *tcg_ctx, TCGv_i32 dest, TCGv_i32 t0, TCGv_`
`452`	`452`	`tcg_gen_subi_i32(tcg_ctx, dest, dest, 1);`
`453`	`453`	`}`
`454`	`454`
`455`		`-static inline void mb_tcg_opcode_cmp_hook(TCGContext *tcg_ctx, TCGv_i64 v0, TCGv_i64 v1, uint32_t size)`
	`455`	`+static inline void mb_tcg_opcode_cmp_hook(TCGContext *tcg_ctx, TCGv_i64 v0, TCGv_i64 v1, uint32_t size, uint32_t pc)`
`456`	`456`	`{`
`457`	`457`	`uc_engine *uc = tcg_ctx->uc;`
`458`	`458`	`if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_TCG_OPCODE, tcg_ctx->pc_start)) {`
`@@ -10925,6 +10925,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)`
`10925`	`10925`	`{`
`10926`	`10926`	`unsigned int cond = insn >> 28;`
`10927`	`10927`	`TCGContext *tcg_ctx = s->uc->tcg_ctx;`
	`10928`	`+ tcg_ctx->pc_start = s->pc_curr;`
`10928`	`10929`
`10929`	`10930`	`/* M variants do not implement ARM mode; this must raise the INVSTATE`
`10930`	`10931`	`* UsageFault exception.`