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Merge elicn's work
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‎bindings/python/README.md

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# Python Bindings for Unicorn
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Originally written by Nguyen Anh Quynh, polished and redesigned by elicn, maintained by all community contributors.
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## Install
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Install a prebuilt wheel from PyPI:

‎bindings/python/sample_all.sh

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#!/bin/sh
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./sample_x86.py
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python3 ./sample_arm.py
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echo "=========================="
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./shellcode.py
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python3 ./sample_armeb.py
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echo "=========================="
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./sample_arm.py
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python3 ./sample_arm64.py
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echo "=========================="
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./sample_arm64.py
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python3 ./sample_arm64eb.py
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echo "=========================="
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./sample_mips.py
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python3 ./sample_m68k.py
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echo "=========================="
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./sample_sparc.py
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python3 ./sample_mips.py
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echo "=========================="
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./sample_m68k.py
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python3 ./sample_ppc.py
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echo "=========================="
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python3 ./sample_riscv.py
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echo "=========================="
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python3 ./sample_s390x.py
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echo "=========================="
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python3 ./sample_sparc.py
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echo "=========================="
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python3 ./sample_tricore.py
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echo "=========================="
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python3 ./sample_x86.py
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echo "=========================="
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python3 ./shellcode.py
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echo "=========================="
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python3 ./sample_ctl.py

‎bindings/python/sample_ctl.py

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# By Lazymio(@wtdcode), 2021
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from unicorn import *
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from unicorn.unicorn import UC_HOOK_EDGE_GEN_CB
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from unicorn.x86_const import *
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from datetime import datetime
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@@ -58,7 +57,7 @@ def test_uc_ctl_tb_cache():
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# Now we clear cache for all TBs.
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for i in range(8):
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uc.ctl_remove_cache(addr + i * 512, addr + i * 512 + 1)
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evicted = time_emulation(uc, addr, addr + len(code))
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print(f">>> Run time: First time {standard}, Cached: {cached}, Cached evicted: {evicted}")
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uc.hook_add(UC_HOOK_EDGE_GENERATED, trace_new_edge)
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# Trace cmp instruction.
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uc.hook_add(UC_HOOK_TCG_OPCODE, trace_tcg_sub, UC_TCG_OP_SUB, UC_TCG_OP_FLAG_CMP)
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uc.hook_add(UC_HOOK_TCG_OPCODE, trace_tcg_sub, aux1=UC_TCG_OP_SUB, aux2=UC_TCG_OP_FLAG_CMP)
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uc.ctl_exits_enabled(True)
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‎bindings/python/unicorn/__init__.py

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# Unicorn Python bindings, by Nguyen Anh Quynnh <[email protected]>
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# Forwarding defs for compatibility
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from . import arm_const, arm64_const, mips_const, sparc_const, m68k_const, x86_const, riscv_const, s390x_const, tricore_const
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from .unicorn_const import *
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from .unicorn import Uc, uc_version, uc_arch_supported, version_bind, debug, UcError, __version__
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from .unicorn import Uc, ucsubclass, uc_version, uc_arch_supported, version_bind, debug, UcError, __version__

‎bindings/python/unicorn/unicorn.py

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else:
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from .unicorn_py3 import *
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__version__ = "%u.%u.%u" % (uc.UC_VERSION_MAJOR, uc.UC_VERSION_MINOR, uc.UC_VERSION_PATCH)
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__version__ = "%u.%u.%u" % (uc.UC_VERSION_MAJOR, uc.UC_VERSION_MINOR, uc.UC_VERSION_PATCH)

‎bindings/python/unicorn/unicorn_py3/__init__.py

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from .unicorn import *
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from .unicorn import *

‎bindings/python/unicorn/unicorn_py3/arch/__init__.py

Whitespace-only changes.

‎bindings/python/unicorn/unicorn_py3/arch/arm.py

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# AArch32 classes and structures.
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#
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# @author elicn
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from typing import Any, Tuple
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import ctypes
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from .. import Uc
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from .. import arm_const as const
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from .types import UcTupledReg, UcReg128
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ARMCPReg = Tuple[int, int, int, int, int, int, int, int]
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class UcRegCP(UcTupledReg[ARMCPReg]):
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"""ARM coprocessors registers for instructions MRC, MCR, MRRC, MCRR
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"""
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_fields_ = (
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('cp', ctypes.c_uint32),
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('is64', ctypes.c_uint32),
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('sec', ctypes.c_uint32),
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('crn', ctypes.c_uint32),
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('crm', ctypes.c_uint32),
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('opc1', ctypes.c_uint32),
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('opc2', ctypes.c_uint32),
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('val', ctypes.c_uint64)
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)
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@property
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def value(self) -> int:
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return self.val
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class UcAArch32(Uc):
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"""Unicorn subclass for ARM architecture.
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"""
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REG_RANGE_Q = range(const.UC_ARM_REG_Q0, const.UC_ARM_REG_Q15 + 1)
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@staticmethod
44+
def __select_reg_class(reg_id: int):
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"""Select class for special architectural registers.
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"""
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reg_class = (
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(UcAArch32.REG_RANGE_Q, UcReg128),
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)
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return next((cls for rng, cls in reg_class if reg_id in rng), None)
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def reg_read(self, reg_id: int, aux: Any = None):
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# select register class for special cases
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reg_cls = UcAArch32.__select_reg_class(reg_id)
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if reg_cls is None:
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if reg_id == const.UC_ARM_REG_CP_REG:
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return self._reg_read(reg_id, UcRegCP, *aux)
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else:
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# fallback to default reading method
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return super().reg_read(reg_id, aux)
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return self._reg_read(reg_id, reg_cls)
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def reg_write(self, reg_id: int, value) -> None:
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# select register class for special cases
70+
reg_cls = UcAArch32.__select_reg_class(reg_id)
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72+
if reg_cls is None:
73+
if reg_id == const.UC_ARM_REG_CP_REG:
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self._reg_write(reg_id, UcRegCP, value)
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else:
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# fallback to default writing method
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super().reg_write(reg_id, value)
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else:
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self._reg_write(reg_id, reg_cls, value)

‎bindings/python/unicorn/unicorn_py3/arch/arm64.py

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# AArch64 classes and structures.
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#
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# @author elicn
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5+
from typing import Any, Callable, NamedTuple, Tuple
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import ctypes
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9+
from .. import Uc, UcError
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from .. import arm64_const as const
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12+
from ..unicorn import uccallback
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from unicorn import UC_ERR_ARG, UC_HOOK_INSN
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from .types import uc_engine, UcTupledReg, UcReg128
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ARM64CPReg = Tuple[int, int, int, int, int, int]
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18+
HOOK_INSN_SYS_CFUNC = ctypes.CFUNCTYPE(ctypes.c_uint32, uc_engine, ctypes.c_uint32, ctypes.c_void_p, ctypes.c_void_p)
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21+
class UcRegCP(UcTupledReg[ARM64CPReg]):
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"""ARM64 coprocessors registers for instructions MRS, MSR
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"""
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25+
_fields_ = (
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('crn', ctypes.c_uint32),
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('crm', ctypes.c_uint32),
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('op0', ctypes.c_uint32),
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('op1', ctypes.c_uint32),
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('op2', ctypes.c_uint32),
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('val', ctypes.c_uint64)
32+
)
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34+
@property
35+
def value(self) -> int:
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return self.val
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class UcAArch64(Uc):
40+
"""Unicorn subclass for ARM64 architecture.
41+
"""
42+
43+
REG_RANGE_Q = range(const.UC_ARM64_REG_Q0, const.UC_ARM64_REG_Q31 + 1)
44+
REG_RANGE_V = range(const.UC_ARM64_REG_V0, const.UC_ARM64_REG_V31 + 1)
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46+
def hook_add(self, htype: int, callback: Callable, user_data: Any = None, begin: int = 1, end: int = 0, aux1: int = 0, aux2: int = 0) -> int:
47+
if htype != UC_HOOK_INSN:
48+
return super().hook_add(htype, callback, user_data, begin, end, aux1, aux2)
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50+
insn = ctypes.c_int(aux1)
51+
52+
def __hook_insn_sys():
53+
@uccallback(HOOK_INSN_SYS_CFUNC)
54+
def __hook_insn_sys_cb(handle: int, reg: int, pcp_reg: Any, key: int) -> int:
55+
cp_reg = ctypes.cast(pcp_reg, ctypes.POINTER(UcRegCP)).contents
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57+
class CpReg(NamedTuple):
58+
crn: int
59+
crm: int
60+
op0: int
61+
op1: int
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op2: int
63+
val: int
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65+
cp_reg = CpReg(cp_reg.crn, cp_reg.crm, cp_reg.op0, cp_reg.op1, cp_reg.op2, cp_reg.val)
66+
67+
return callback(self, reg, cp_reg, user_data)
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69+
return __hook_insn_sys_cb
70+
71+
handlers = {
72+
const.UC_ARM64_INS_MRS : __hook_insn_sys,
73+
const.UC_ARM64_INS_MSR : __hook_insn_sys,
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const.UC_ARM64_INS_SYS : __hook_insn_sys,
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const.UC_ARM64_INS_SYSL : __hook_insn_sys
76+
}
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78+
handler = handlers.get(insn.value)
79+
80+
if handler is None:
81+
raise UcError(UC_ERR_ARG)
82+
83+
fptr = handler()
84+
85+
return getattr(self, '_Uc__do_hook_add')(htype, fptr, begin, end, insn)
86+
87+
@staticmethod
88+
def __select_reg_class(reg_id: int):
89+
"""Select class for special architectural registers.
90+
"""
91+
92+
reg_class = (
93+
(UcAArch64.REG_RANGE_Q, UcReg128),
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(UcAArch64.REG_RANGE_V, UcReg128)
95+
)
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97+
return next((cls for rng, cls in reg_class if reg_id in rng), None)
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def reg_read(self, reg_id: int, aux: Any = None):
100+
# select register class for special cases
101+
reg_cls = UcAArch64.__select_reg_class(reg_id)
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103+
if reg_cls is None:
104+
if reg_id == const.UC_ARM64_REG_CP_REG:
105+
return self._reg_read(reg_id, UcRegCP, *aux)
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107+
else:
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# fallback to default reading method
109+
return super().reg_read(reg_id, aux)
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return self._reg_read(reg_id, reg_cls)
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def reg_write(self, reg_id: int, value) -> None:
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# select register class for special cases
115+
reg_cls = UcAArch64.__select_reg_class(reg_id)
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117+
if reg_cls is None:
118+
if reg_id == const.UC_ARM64_REG_CP_REG:
119+
self._reg_write(reg_id, UcRegCP, value)
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else:
122+
# fallback to default writing method
123+
super().reg_write(reg_id, value)
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125+
else:
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self._reg_write(reg_id, reg_cls, value)

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