@@ -39,7 +39,7 @@ def test_uc_ctl_tb_cache():
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# Fill the code buffer with NOP.
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code = b"\x90 " * 8 * 512
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- print ("Controling the TB cache in a finer granularity by uc_ctl." )
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+ print ("Controlling the TB cache in a finer granularity by uc_ctl." )
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uc .mem_map (addr , 0x10000 )
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@@ -52,7 +52,7 @@ def test_uc_ctl_tb_cache():
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# Now we request cache for all TBs.
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for i in range (8 ):
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tb = uc .ctl_request_cache (addr + i * 512 )
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- print (f">>> TB is cached at { hex (tb . pc )} which has { tb . icount } instructions with { tb . size } bytes" )
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+ print (f">>> TB is cached at { hex (tb [ 0 ] )} which has { tb [ 1 ] } instructions with { tb [ 2 ] } bytes" )
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# Do emulation with all TB cached.
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cached = time_emulation (uc , addr , addr + len (code ))
@@ -104,15 +104,15 @@ def test_uc_ctl_exits():
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uc .ctl_set_exits (exits )
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- # This should stop at ADDRESS + 6 and increase eax, even thouhg we don't provide an exit.
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+ # This should stop at ADDRESS + 6 and increase eax, even though we don't provide an exit.
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uc .emu_start (addr , 0 )
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eax = uc .reg_read (UC_X86_REG_EAX )
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ebx = uc .reg_read (UC_X86_REG_EBX )
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print (f">>> eax = { hex (eax )} and ebx = { hex (ebx )} after the first emulation" )
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- # This should stop at ADDRESS + 8, even thouhg we don't provide an exit.
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+ # This should stop at ADDRESS + 8, even though we don't provide an exit.
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uc .emu_start (addr , 0 )
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eax = uc .reg_read (UC_X86_REG_EAX )
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