@@ -97,6 +97,30 @@ static void test_mips_stop_at_delay_slot(void)
97
97
OK (uc_close (uc ));
98
98
}
99
99
100
+ static void test_mips_stop_delay_slot_from_qiling (void )
101
+ {
102
+ uc_engine * uc ;
103
+ // 24 06 00 03 addiu $a2, $zero, 3
104
+ // 10 a6 00 79 beq $a1, $a2, 0x47c8da4
105
+ // 30 42 00 fc andi $v0, $v0, 0xfc
106
+ char code [] =
107
+ "\x24\x06\x00\x03\x10\xa6\x00\x79\x30\x42\x00\xfc" ;
108
+ uint32_t r_pc = 0x0 ;
109
+ uint32_t r_a2 = 1 ;
110
+
111
+ uc_common_setup (& uc , UC_ARCH_MIPS , UC_MODE_MIPS32 | UC_MODE_BIG_ENDIAN ,
112
+ code , sizeof (code ) - 1 );
113
+
114
+ OK (uc_reg_write (uc , UC_MIPS_REG_A2 , & r_a2 ));
115
+
116
+ OK (uc_emu_start (uc , code_start , code_start + sizeof (code ) - 1 , 0 , 2 ));
117
+
118
+ OK (uc_reg_read (uc , UC_MIPS_REG_PC , & r_pc ));
119
+ TEST_CHECK (r_pc == code_start + 12 );
120
+
121
+ OK (uc_close (uc ));
122
+ }
123
+
100
124
static void test_mips_lwx_exception_issue_1314 (void )
101
125
{
102
126
uc_engine * uc ;
@@ -176,4 +200,5 @@ TEST_LIST = {
176
200
{"test_mips_lwx_exception_issue_1314" , test_mips_lwx_exception_issue_1314 },
177
201
{"test_mips_mips16" , test_mips_mips16 },
178
202
{"test_mips_mips_fpr" , test_mips_mips_fpr },
203
+ {"test_mips_stop_delay_slot_from_qiling" , test_mips_stop_delay_slot_from_qiling },
179
204
{NULL , NULL }};
0 commit comments