Merge pull request #1991 from apparentlymart/b-riscv-invalidinsn-pcadj

wtdcode · web-flow · commit 9427f0a55382 · 2024-09-21T18:26:59.000+08:00
riscv: Invalid 32-bit instruction should not decrement pc
diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c
@@ -769,7 +769,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                              translator_lduw(tcg_ctx, env, ctx->base.pc_next + 2));
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, opcode32)) {
-            ctx->pc_succ_insn = ctx->base.pc_next - 4;
             gen_exception_illegal(ctx);
         }
     }

Original file line number	Diff line number	Diff line change
`@@ -769,7 +769,6 @@ static void decode_opc(CPURISCVState env, DisasContext ctx, uint16_t opcode)`
`769`	`769`	`translator_lduw(tcg_ctx, env, ctx->base.pc_next + 2));`
`770`	`770`	`ctx->pc_succ_insn = ctx->base.pc_next + 4;`
`771`	`771`	`if (!decode_insn32(ctx, opcode32)) {`
`772`		`- ctx->pc_succ_insn = ctx->base.pc_next - 4;`
`773`	`772`	`gen_exception_illegal(ctx);`
`774`	`773`	`}`
`775`	`774`	`}`