v0.12.0-esp32-20250226

Features:

• target/esp32[c5|c6|c61|h2]: Exposed user CSRs.
• target/esp32[c5|c61|p4]: Added support for memory protection.
• target/esp32[c5|61]: Configured debug assistant address
• target/riscv: add flag to pause sending events to GDB. OpenOCD can halt and resume the target to implement some features. This kind of internal events should not be reported to GDB. Otherwise gdb might stop unintentionally and asks for register read, and remove breakpoints when the target is running.
• rtos/nuttx: Added missing Espressif riscv targets: esp32[c2|c5|c6|c61|h2|p4]
• rtos/nuttx: Added TIE registers support for esp32s3.
• rtos/zephyr: Added Espressif targets esp32[c5|c61|p4].
• rtos/freertos: Added support for non-default FreeRTOS list structure fields offsets, e.g. when CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES is enabled in IDF config. Read them at runtime from target.
• contrib/loaders: Added support for MCU boot image format. Close #243
• contrib/loaders: Added support for Simple boot used by Nuttx and Zephyr.
• contrib/loaders: Added flasher stub's clock boost support for esp32[c5|c61|p4]
• tcl/esp_common: Added option for program_esp[_bins] to skip flashing the same binary.
• esp: Added a problem hints file to the distribution. It is intended for IDEs to suggest possible solutions to users based on error output in the OpenOCD log.

Fixes:

• target/esp32p4: Custom mintstatus declaration due to the changed register number. Can be accessed as csr_mintstatus.
• target/esp32p4: Fixed memory access; only perform writeback for DCACHE only.
• target/esp32p4: Set watchpoints on both cores; previously, watchpoints were set only on the active core.
• target/esp32p4: Avoid writeback/invalidate all cache memory. Do it according to cache line size.
• target/esp32s3: Fixed DROM memory boundaries.
• target/esp32: Fixed incorrect sampling of the ESP32 bootstrap pin GPIO12. When the flash is empty, the TDI pin remains floating and may be sampled at an incorrect level by the bootstrap circuit, which can cause the flash to operate at an unexpected voltage.
• target/xtensa: Reset the powered-off counter when an unexamined target is powered on, so that it can be polled to detect if it becomes active later on.
• target/riscv: Update mstatus.*ie bits only with set_maskisr steponly. When value of mstatus CSR changes while stepping with set_maskisr steponly, OpenOCD should not write back the old value to mstatus when reenabling interrupts.
• target/riscv: Reset dm after unexpected resets
• target/espressif: Clear algorithm state in case of a timeout. Fixes false Target is already running an algorithm error.
• rtos/nuttx: Fixed thread details query when OS is not initialized yet. Check g_nx_initstate before providing thread details.
• rtos/freertos: Fix incorrect register values returned in p packet for ESP32-C* (RISC-V) on FreeRTOS. Close #352
• rtos/freertos: Added several sanity checks when reading the symbol table from the target.
• flash/esp: Increase hash calculation algorithm timeout to 30 sec. If the targets don't yet have clock boost functionality, reading flash through the cache takes longer than accessing the flash directly—likely due to the cache_suspend, cache_resume, and cache_invalidation functions. As a result, the previous 3-second verification timeout was insufficient for the C5, as the customer's binary takes 3.2 seconds to verify.
• target/esp_semihosting: Fixed the WSL mingw64 build error. Close #347.
• target/esp32p4: Invalidated L2 cache during cache flush in the stub flasher, improving flash breakpoint hit reliability.
• target/esp32p4: Fixed ESP_RTOS variable setting. It was previously impossible to assign any value other than FreeRTOS.
• target/esp32p4: Fixed re-examination issue after hard reset of target.
• target/esp32p4: Unstall hart0 before issuing the reset; this fixes the reset issue on halted targets caused by exceptions.

Other:

• Synced with upstream.
• tcl/esp: Make usage of esp32_devkitj_v1.cfg deprecated in favor of esp_ftdi.cfg for all Espressif FTDI dev kits.

Known issues:

• target/esp32c[5|61]: Temporarily disabled access to some user registers to avoid GDB errors. Registers are cycle, time, instreth, cycleh, instret, timeh, hpmcounter8, hpmcounter9, hpmcounter13, hpmcounter8h, hpmcounter9h, hpmcounter13h.