Merge pull request #2003 from elicn/dev

Misc. Python binding re-arrangements

Author: wtdcode

bindings/python/sample_all.sh

@@ -27,3 +27,5 @@ echo "=========================="
 python3 ./shellcode.py
 echo "=========================="
 python3 ./sample_ctl.py
+echo "=========================="
+python3 ./sample_network_auditing.py

bindings/python/unicorn/unicorn.py

@@ -1,8 +1,14 @@
-import sys
+import sys as _sys
 
-if sys.version_info[0] == 2:
+from .unicorn_const import (
+    UC_VERSION_MAJOR as __MAJOR,
+    UC_VERSION_MINOR as __MINOR,
+    UC_VERSION_PATCH as __PATCH
+)
+
+__version__ = "%u.%u.%u" % (__MAJOR, __MINOR, __PATCH)
+
+if _sys.version_info.major == 2:
     from .unicorn_py2 import *
 else:
     from .unicorn_py3 import *
-
-__version__ = "%u.%u.%u" % (uc.UC_VERSION_MAJOR, uc.UC_VERSION_MINOR, uc.UC_VERSION_PATCH)

bindings/python/unicorn/unicorn_py3/arch/__init__.py

@@ -1,4 +0,0 @@
-# from .arm import UcRegCP
-# from .arm64 import UcRegCP64
-# from .intel import UcRegFPR, UcRegMMR, UcRegMSR
-# from .types import UcReg128, UcReg256, UcReg512, UcReg, UcLargeReg, UcTupledReg

bindings/python/unicorn/unicorn_py3/arch/arm.py

@@ -1,21 +1,20 @@
-# AArch32 classes and structures.
-#
+"""AArch32 classes and structures.
+"""
 # @author elicn
 
 from typing import Any, Tuple
 
 import ctypes
 
-from .. import Uc
-from .. import arm_const as const
+# traditional unicorn imports
+from unicorn import arm_const as const
 
+# newly introduced unicorn imports
+from ..unicorn import Uc
 from .types import UcTupledReg, UcReg128
 
 ARMCPReg = Tuple[int, int, int, int, int, int, int, int]
 
-def _structure_repr(self):
-    return "%s(%s)" % (self.__class__.__name__, ", ".join("%s=%s" % (k, getattr(self, k)) for (k, _) in self._fields_))
-
 
 class UcRegCP(UcTupledReg[ARMCPReg]):
     """ARM coprocessors registers for instructions MRC, MCR, MRRC, MCRR
@@ -36,7 +35,6 @@ class UcRegCP(UcTupledReg[ARMCPReg]):
     def value(self) -> int:
         return self.val
 
-    __repr__ = _structure_repr
 
 class UcAArch32(Uc):
     """Unicorn subclass for ARM architecture.
@@ -83,3 +81,5 @@ def reg_write(self, reg_id: int, value) -> None:
 
         else:
             self._reg_write(reg_id, reg_cls, value)
+
+__all__ = ['UcRegCP', 'UcAArch32']

bindings/python/unicorn/unicorn_py3/arch/arm64.py

@@ -1,16 +1,17 @@
-# AArch64 classes and structures.
-#
+"""AArch64 classes and structures.
+"""
 # @author elicn
 
 from typing import Any, Callable, NamedTuple, Tuple
 
 import ctypes
 
-from .. import Uc, UcError
-from .. import arm64_const as const
+# traditional unicorn imports
+from unicorn import arm64_const as const
+from unicorn.unicorn_const import UC_ERR_ARG, UC_HOOK_INSN
 
-from ..unicorn import uccallback
-from unicorn import UC_ERR_ARG, UC_HOOK_INSN
+# newly introduced unicorn imports
+from ..unicorn import Uc, UcError, uccallback
 from .types import uc_engine, UcTupledReg, UcReg128
 
 ARM64CPReg = Tuple[int, int, int, int, int, int]
@@ -124,3 +125,5 @@ def reg_write(self, reg_id: int, value) -> None:
 
         else:
             self._reg_write(reg_id, reg_cls, value)
+
+__all__ = ['UcRegCP64', 'UcAArch64']

bindings/python/unicorn/unicorn_py3/arch/intel.py

@@ -1,16 +1,17 @@
-# Intel architecture classes and structures.
-#
+"""Intel architecture classes and structures.
+"""
 # @author elicn
 
-from typing import Any, Callable, Tuple
+from typing import Any, Callable, Sequence, Tuple
 
 import ctypes
 
-from .. import Uc, UcError
-from .. import x86_const as const
-
-from unicorn.unicorn_py3 import uccallback
+# traditional unicorn imports
+from unicorn import x86_const as const
 from unicorn.unicorn_const import UC_ERR_ARG, UC_HOOK_INSN
+
+# newly introduced unicorn imports
+from ..unicorn import Uc, UcError, uccallback
 from .types import uc_engine, UcTupledReg, UcReg128, UcReg256, UcReg512
 
 X86MMRReg = Tuple[int, int, int, int]
@@ -36,6 +37,9 @@ class UcRegMMR(UcTupledReg[X86MMRReg]):
 
 
 class UcRegMSR(UcTupledReg[X86MSRReg]):
+    """Intel Model Specific Register
+    """
+
     _fields_ = (
         ('rid', ctypes.c_uint32),
         ('val', ctypes.c_uint64)
@@ -47,6 +51,9 @@ def value(self) -> int:
 
 
 class UcRegFPR(UcTupledReg[X86FPReg]):
+    """Intel Floating Point Register
+    """
+
     _fields_ = (
         ('mantissa', ctypes.c_uint64),
         ('exponent', ctypes.c_uint16)
@@ -176,3 +183,11 @@ def msr_read(self, msr_id: int) -> int:
 
     def msr_write(self, msr_id: int, value: int) -> None:
         self._reg_write(const.UC_X86_REG_MSR, UcRegMSR, (msr_id, value))
+
+    def reg_read_batch(self, reg_ids: Sequence[int]) -> Tuple:
+        reg_types = [UcIntel.__select_reg_class(rid) or self._DEFAULT_REGTYPE for rid in reg_ids]
+
+        return self._reg_read_batch(reg_ids, reg_types)
+
+
+__all__ = ['UcRegMMR', 'UcRegMSR', 'UcRegFPR', 'UcIntel']

bindings/python/unicorn/unicorn_py3/arch/types.py

@@ -1,5 +1,5 @@
-# Common types and structures.
-#
+"""Common types and structures.
+"""
 # @author elicn
 
 from abc import abstractmethod
@@ -15,9 +15,6 @@
 
 VT = TypeVar('VT', bound=Tuple[int, ...])
 
-def _structure_repr(self):
-    return "%s(%s)" % (self.__class__.__name__, ", ".join("%s=%s" % (k, getattr(self, k)) for (k, _) in self._fields_))
-
 
 class UcReg(ctypes.Structure):
     """A base class for composite registers.
@@ -41,7 +38,6 @@ def from_value(cls, value):
 
         pass
 
-    _repr_ = _structure_repr
 
 class UcTupledReg(UcReg, Generic[VT]):
     """A base class for registers whose values are represented as a set
@@ -85,12 +81,24 @@ def from_value(cls, value: int):
 
 
 class UcReg128(UcLargeReg):
+    """Large register holding a 128-bit value.
+    """
+
     _fields_ = [('qwords', ctypes.c_uint64 * 2)]
 
 
 class UcReg256(UcLargeReg):
+    """Large register holding a 256-bit value.
+    """
+
     _fields_ = [('qwords', ctypes.c_uint64 * 4)]
 
 
 class UcReg512(UcLargeReg):
+    """Large register holding a 512-bit value.
+    """
+
     _fields_ = [('qwords', ctypes.c_uint64 * 8)]
+
+
+__all__ = ['uc_err', 'uc_engine', 'uc_context', 'uc_hook_h', 'UcReg', 'UcTupledReg', 'UcLargeReg', 'UcReg128', 'UcReg256', 'UcReg512']