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7 files changed

+39
-33
lines changed

7 files changed

+39
-33
lines changed

‎include/unicorn/mips.h

+2-1
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,8 @@ typedef enum UC_MIPS_REG {
220220
UC_MIPS_REG_CP0_USERLOCAL,
221221
UC_MIPS_REG_CP0_STATUS,
222222

223-
// FCR(s) Ref: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00083-2B-MIPS64INT-AFP-06.01.pdf
223+
// FCR(s) Ref:
224+
// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00083-2B-MIPS64INT-AFP-06.01.pdf
224225
UC_MIPS_REG_FIR,
225226
UC_MIPS_REG_FCSR,
226227

‎include/unicorn/unicorn.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ typedef size_t uc_hook;
6565
#define UNICORN_DEPRECATED __declspec(deprecated)
6666
#else
6767
#pragma message( \
68-
"WARNING: You need to implement UNICORN_DEPRECATED for this compiler")
68+
"WARNING: You need to implement UNICORN_DEPRECATED for this compiler")
6969
#define UNICORN_DEPRECATED
7070
#endif
7171

‎qemu/target/mips/unicorn.c

+7-5
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,8 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc);
1919

2020
static void mips_set_pc(struct uc_struct *uc, uint64_t address)
2121
{
22-
((CPUMIPSState *)uc->cpu->env_ptr)->active_tc.PC = address & ~(uint64_t )1ULL;
22+
((CPUMIPSState *)uc->cpu->env_ptr)->active_tc.PC =
23+
address & ~(uint64_t)1ULL;
2324
if (address & 1) {
2425
((CPUMIPSState *)uc->cpu->env_ptr)->hflags |= MIPS_HFLAG_M16;
2526
} else {
@@ -30,7 +31,7 @@ static void mips_set_pc(struct uc_struct *uc, uint64_t address)
3031
static uint64_t mips_get_pc(struct uc_struct *uc)
3132
{
3233
return ((CPUMIPSState *)uc->cpu->env_ptr)->active_tc.PC |
33-
!!(((CPUMIPSState *)uc->cpu->env_ptr)->hflags & (MIPS_HFLAG_M16));
34+
!!(((CPUMIPSState *)uc->cpu->env_ptr)->hflags & (MIPS_HFLAG_M16));
3435
}
3536

3637
static void mips_release(void *ctx)
@@ -234,14 +235,15 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
234235
case UC_MIPS_REG_F30:
235236
case UC_MIPS_REG_F31:
236237
CHECK_REG_TYPE(uint64_t);
237-
env->active_fpu.fpr[regid - UC_MIPS_REG_F0].d = *(uint64_t*)value;
238+
env->active_fpu.fpr[regid - UC_MIPS_REG_F0].d = *(uint64_t *)value;
238239
break;
239240
case UC_MIPS_REG_FCSR: {
240241
CHECK_REG_TYPE(uint32_t);
241242
uint32_t arg1 = *(uint32_t *)value;
242243
uint32_t original = env->active_fpu.fcr31;
243-
env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
244-
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
244+
env->active_fpu.fcr31 =
245+
(arg1 & env->active_fpu.fcr31_rw_bitmask) |
246+
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
245247
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
246248
GET_FP_CAUSE(env->active_fpu.fcr31)) {
247249
env->active_fpu.fcr31 = original;

‎tests/unit/test_arm.c

+4-3
Original file line numberDiff line numberDiff line change
@@ -764,8 +764,8 @@ static void test_arm_context_save(void)
764764

765765
OK(uc_context_alloc(uc, &ctx));
766766
OK(uc_context_save(uc, ctx));
767-
OK(uc_context_reg_read(ctx, UC_ARM_REG_PC, (void*)&pc));
768-
OK(uc_context_reg_write(ctx, UC_ARM_REG_PC, (void*)&pc));
767+
OK(uc_context_reg_read(ctx, UC_ARM_REG_PC, (void *)&pc));
768+
OK(uc_context_reg_write(ctx, UC_ARM_REG_PC, (void *)&pc));
769769
OK(uc_context_restore(uc, ctx));
770770

771771
uc_common_setup(&uc2, UC_ARCH_ARM, UC_MODE_THUMB, code, sizeof(code) - 1,
@@ -841,7 +841,8 @@ static void test_arm_mem_hook_read_write(void)
841841
// str r1, [sp, #4]
842842
// ldr r2, [sp, #4]
843843
// str r2, [sp]
844-
const char code[] = "\x00\x10\x9d\xe5\x04\x10\x8d\xe5\x04\x20\x9d\xe5\x00\x20\x8d\xe5";
844+
const char code[] =
845+
"\x00\x10\x9d\xe5\x04\x10\x8d\xe5\x04\x20\x9d\xe5\x00\x20\x8d\xe5";
845846
uint32_t r_sp;
846847
r_sp = 0x9000;
847848
uc_hook hk;

‎tests/unit/test_arm64.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ static void test_arm64_block_sync_pc_cb(uc_engine *uc, uint64_t addr,
300300
uint32_t size, void *data)
301301
{
302302
uint64_t pc;
303-
OK(uc_reg_read(uc, UC_ARM64_REG_PC, (void*)&pc));
303+
OK(uc_reg_read(uc, UC_ARM64_REG_PC, (void *)&pc));
304304
TEST_CHECK(pc == addr);
305305
uint64_t val = code_start;
306306
bool first = *(bool *)data;

‎tests/unit/test_mips.c

+14-13
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ static void test_mips_el_ori(void)
1717
char code[] = "\x56\x34\x21\x34"; // ori $at, $at, 0x3456;
1818
int r_r1 = 0x6789;
1919

20-
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, code,
21-
sizeof(code) - 1);
20+
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN,
21+
code, sizeof(code) - 1);
2222
OK(uc_reg_write(uc, UC_MIPS_REG_1, &r_r1));
2323

2424
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
@@ -36,8 +36,8 @@ static void test_mips_eb_ori(void)
3636
char code[] = "\x34\x21\x34\x56"; // ori $at, $at, 0x3456;
3737
int r_r1 = 0x6789;
3838

39-
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_BIG_ENDIAN, code,
40-
sizeof(code) - 1);
39+
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_BIG_ENDIAN,
40+
code, sizeof(code) - 1);
4141
OK(uc_reg_write(uc, UC_MIPS_REG_1, &r_r1));
4242

4343
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
@@ -56,8 +56,8 @@ static void test_mips_stop_at_branch(void)
5656
"\x02\x00\x00\x08\x00\x00\x00\x00\x00\x00\x00\x00"; // j 0x8; nop;
5757
int r_pc = 0x0;
5858

59-
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, code,
60-
sizeof(code) - 1);
59+
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN,
60+
code, sizeof(code) - 1);
6161

6262
// Execute one instruction with branch delay slot.
6363
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 1));
@@ -78,8 +78,8 @@ static void test_mips_stop_at_delay_slot(void)
7878
"\x02\x00\x00\x08\x00\x00\x00\x00\x00\x00\x00\x00"; // j 0x8; nop;
7979
int r_pc = 0x0;
8080

81-
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, code,
82-
sizeof(code) - 1);
81+
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN,
82+
code, sizeof(code) - 1);
8383

8484
// Stop at the delay slot by design.
8585
OK(uc_emu_start(uc, code_start, code_start + 4, 0, 0));
@@ -99,8 +99,8 @@ static void test_mips_lwx_exception_issue_1314(void)
9999
char code[] = "\x0a\xc8\x79\x7e"; // lwx $t9, $t9($s3)
100100
int reg;
101101

102-
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, code,
103-
sizeof(code) - 1);
102+
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN,
103+
code, sizeof(code) - 1);
104104
OK(uc_mem_map(uc, 0x10000, 0x4000, UC_PROT_ALL));
105105

106106
// Enable DSP
@@ -133,11 +133,12 @@ static void test_mips_mips16(void)
133133
int r_v0 = 0x6789;
134134
int mips16_lowbit = 1;
135135

136-
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, code,
137-
sizeof(code) - 1);
136+
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN,
137+
code, sizeof(code) - 1);
138138
OK(uc_reg_write(uc, UC_MIPS_REG_V0, &r_v0));
139139

140-
OK(uc_emu_start(uc, code_start | mips16_lowbit, code_start + sizeof(code) - 1, 0, 0));
140+
OK(uc_emu_start(uc, code_start | mips16_lowbit,
141+
code_start + sizeof(code) - 1, 0, 0));
141142

142143
OK(uc_reg_read(uc, UC_MIPS_REG_V0, &r_v0));
143144

‎tests/unit/unicorn_test.h

+10-9
Original file line numberDiff line numberDiff line change
@@ -11,18 +11,19 @@
1111

1212
/* Swap bytes in 32 bit value. */
1313
#define bswap_32(x) \
14-
((((x)&0xff000000u) >> 24) | (((x)&0x00ff0000u) >> 8) | \
15-
(((x)&0x0000ff00u) << 8) | (((x)&0x000000ffu) << 24))
14+
((((x) & 0xff000000u) >> 24) | (((x) & 0x00ff0000u) >> 8) | \
15+
(((x) & 0x0000ff00u) << 8) | (((x) & 0x000000ffu) << 24))
1616

1717
/* Swap bytes in 64 bit value. */
1818
#define bswap_64(x) \
19-
((((x)&0xff00000000000000ull) >> 56) | \
20-
(((x)&0x00ff000000000000ull) >> 40) | \
21-
(((x)&0x0000ff0000000000ull) >> 24) | \
22-
(((x)&0x000000ff00000000ull) >> 8) | (((x)&0x00000000ff000000ull) << 8) | \
23-
(((x)&0x0000000000ff0000ull) << 24) | \
24-
(((x)&0x000000000000ff00ull) << 40) | \
25-
(((x)&0x00000000000000ffull) << 56))
19+
((((x) & 0xff00000000000000ull) >> 56) | \
20+
(((x) & 0x00ff000000000000ull) >> 40) | \
21+
(((x) & 0x0000ff0000000000ull) >> 24) | \
22+
(((x) & 0x000000ff00000000ull) >> 8) | \
23+
(((x) & 0x00000000ff000000ull) << 8) | \
24+
(((x) & 0x0000000000ff0000ull) << 24) | \
25+
(((x) & 0x000000000000ff00ull) << 40) | \
26+
(((x) & 0x00000000000000ffull) << 56))
2627

2728
/**
2829
* Assert that err matches expect

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